Wherever data is transmitted over a long distance, a clock signal must be embedded in the data stream. As long as the transition density is not too low, the receiving system can recover both clock and data effectively.
To perform clock and data recovery from a serial data stream, the conventional approach is to use analog Phase-Locked Loops and Delay-Locked Loops as well as digital Phase-Locked Loops and Delay-Locked Loops. Both oversampling and non-oversampling schemes have been used. In general, prior art oversampling and non-oversampling methods rely on some kind of servo control loop.
In contrast, the present invention uses transitions in the received signal to directly control a digital circuit rather than to adjust a servo system. This new circuit and method is speed scalable and technology portable. The speed can start from very low to adequately high. For example, when implemented as a semiconductor circuit using a standard 0.5 um CMOS process, the present invention can achieve clock and data recovery from a high speed, 125 Mbps data signal. The same circuit structure is also portable to various integrated circuit technologies including BiCMOS, Bipolar, GaAs, GeSi and most other types of digital IC fabrication technology. The present invention works well with any line coding scheme having reasonable transition density.